– Process Flow:
– Stack deposition (oxide + protective nitride)
– Lithography print
– Dry etch (Reactive-ion etching)
– Trench fill with oxide
– Chemical-mechanical polishing of the oxide
– Scaling of Isolation:
– Isolation pitch is the sum of the transistor width and the trench isolation distance
– Narrow channel width effect becomes more apparent as isolation pitch shrinks
– Reverse narrow channel effect due to electric field enhancement at the edge
– Threshold voltage reduction leads to increased subthreshold leakage current
– Deep trench isolation found in analog integrated circuits
– Fabrication Process:
– STI prevents electric current leakage between adjacent semiconductor device components
– STI used on CMOS process technology nodes of 250 nanometers and smaller
– Older technologies use isolation based on LOCOS
– Key steps involve etching trenches, filling with dielectric materials, and planarization
– Deep trench isolation found in analog integrated circuits
– References:
– Quirk & Serda’s Semiconductor Manufacturing Technology
– Jung et al.’s study on reverse narrow channel effect
– Chatterjee et al.’s shallow trench isolation study for CMOS technologies
– Pretet et al.’s study on narrow-channel effects in SOI MOSFETs
– Lee et al.’s research on trench edge impact on pMOSFET reliability
– External Links:
– Clarycon: Shallow trench isolation
– N and K Technologies: Shallow trench isolation (dead link)
– Dow Corning: Spin-on Dielectrics – Spin-on Shallow Trench Isolation
Shallow trench isolation (STI), also known as box isolation technique, is an integrated circuit feature which prevents electric current leakage between adjacent semiconductor device components. STI is generally used on CMOS process technology nodes of 250 nanometers and smaller. Older CMOS technologies and non-MOS technologies commonly use isolation based on LOCOS.
STI is created early during the semiconductor device fabrication process, before transistors are formed. The key steps of the STI process involve etching a pattern of trenches in the silicon, depositing one or more dielectric materials (such as silicon dioxide) to fill the trenches, and removing the excess dielectric using a technique such as chemical-mechanical planarization.[1]
Certain semiconductor fabrication technologies also include deep trench isolation, a related feature often found in analog integrated circuits.
The effect of the trench edge has given rise to what has recently been termed the "reverse narrow channel effect" or "inverse narrow width effect". Basically, due to the electric field enhancement at the edge, it is easier to form a conducting channel (by inversion) at a lower voltage. The threshold voltage is effectively reduced for a narrower transistor width. The main concern for electronic devices is the resulting subthreshold leakage current, which is substantially larger after the threshold voltage reduction.
